Abstract

Abstract

Abstract

Many industrial and scientific applications, ranging from 3D imaging (such as LIDAR, surveillance, object tracking) to Time Correlated Single Photon Counting (TCSPC) require the ability to perform time-resolved detection of weak light signals, down to single-photon level. Single-Photon Avalanche Diodes are solid-state detectors capable of single-photon sensitivity in the visible and near-infrared regions, and are compatible with standard silicon processes. This trend has driven the development of low cost, large size CMOS SPAD imagers.

In this work we present the design and characterization of a time-gated, 32x32 SPAD image sensor realized in a 0.16 µm BCD (Bipolar, CMOS, DMOS) technology. The sensor is based on an innovative 16x16 macropixel structure, each composed of four SPADs with independent front-end and event counters, and a shared Time-to-Digital Converter. This approach allows our design to reach higher fill factor (9.6% with a pixel pitch of 100 µm) by sharing the costly (in terms of area) TDC resource, as well as reducing the power dissipation of the chip itself.

The imager provides simultaneous photon-timing and photon-counting data and features a 12 bit, 75 ps bin-width TDC that can perform one conversion per each gate window, with up to 62 windows per acquisition frame. Two main operation modes are available: a single-photon mode where an arbitration circuit in the macropixel is used to share the TDC with no loss of X-Y resolution, and a two-photon-coincidence mode (intended for rejection of background light) where the TDC performs a conversion only if two SPADs in the macropixel detect a photon within a preset coincidence window.

Lastly, the sensor provides the user with multiple readout modes, which provide varying amount of data to fit different end applications. The imager is capable of 100 kFPS in full readout mode, and up to 400 kFPS if the user selects a reduced data mode.

TitleTime-gated SPAD camera with reconfigurable macropixels for LIDAR applications
ImageImage
Image caption

Layout of the SPAD array chip. Die size is 4.2 x 4.6 mm², with an imaging area of 3.2 x 3.2 mm² and a total active area of about 1 mm².

First nameDavide
Last namePortaluppi
Affiliation

Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy

Additional authors
Session11. SPAD special session II
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